I am a Ph.D. candidate in Computer Science and Engineering at the University of Michigan. My research bridges computer architecture and software systems, demonstrating the importance of that bridge in realizing efficient web services via solutions that span the systems stack.
Modern web services require data centers that scale to hundreds of thousands of servers, i.e., hyperscale. With the end of Moore’s Law and Dennard scaling, system designers must optimize the fundamental performance vs. cost and energy efficiency trade-off. Although systems researchers and architects have long studied this trade-off, its hyperscale effects are less understood. At hyperscale, poor software and hardware design choices, even small ones, can cause a significant trade-off imbalance (e.g., diverse high-performance custom hardware cannot be deployed without losing economies of scale). My research shows that the software/hardware design space for hyperscale systems is too complex to manually identify optimal software/hardware designs. To achieve hyperscale efficiency, my work systematically characterizes software/hardware design space implications at hyperscale, and uses my characterization’s insights to develop scalable full-stack solutions that automatically self-navigate the complex design space. My systems solutions to improve hardware efficiency have been deployed in real hyperscale data centers and currently serve billions of users, saving millions of dollars and significantly reducing the global carbon footprint. Additionally, my hardware design proposals have influenced the design of Intel’s Alder Lake (Golden Cove and future generation) CPU architectures.
I am a recipient of the Facebook Fellowship, a Rackham Merit Ph.D. Fellowship, and a CIS Full-Tuition Scholarship. I was selected for the Rising Stars in EECS Workshop and the Heidelberg Laureate Forum. My research has been recognized with an IEEE Micro Top Picks distinction and has appeared in top computer architecture and systems venues like OSDI, ISCA, ASPLOS, MICRO, and HPCA.
My Ph.D. thesis is advised by Prof. Thomas F. Wenisch. Due to some interesting circumstances this past year, I had the incredible opportunity of working with Prof. David Brooks, Prof. Margo Seltzer, Prof. Peter M. Chen, and Prof. Baris Kasikci, while mentoring some of their students.
I am on the academic job market for tenure-track faculty positions. I expect to graduate in Spring 2021. I am interested in positions both in the US and abroad. Please reach out to me if you are hiring!
PhD in Computer Science, 2021 (expected)
University of Michigan
M.S. in Embedded Systems, 2015
University of Pennsylvania
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In MICRO 2020 (Acceptance rate: 15.6%)
Tanvir Ahmed Khan, Akshitha Sriraman, Joseph Devietti, Gilles Pokam, Heiner Litz, Baris Kasikci
Introduces a novel profile-driven instruction prefetching technique that conditionally prefetches instructions only when the program context is known to lead to misses
In ASPLOS 2020 (Acceptance rate: 18.1%)
Akshitha Sriraman, Abhishek Dhanotia
Comprehensively identifies software and hardware acceleration opportunities in hyperscale microservices and analytically models realistic performance benefits from hardware acceleration
Selected as an IEEE Micro Top Picks paper (awarded to the top 12 computer architecture papers of 2020)
Best Presentation Award
ACM Badges: Artifacts Available and Artifacts Evaluated & Functional
Featured by TechXplore, Debuglies News, Michigan News, and Facebook Engineering
In the Non-Volatile Memories Workshop (NVMW), 2020
Lillian Pentecost, Marco Donato, Akshitha Sriraman, Gu-Yeon Wei, David Brooks
Introduces an analytical model to analyze the large design space available with of emerging memory technologies
In ISCA 2019 (Acceptance rate: 16.9%)
Akshitha Sriraman, Abhishek Dhanotia, Thomas F. Wenisch
First comprehensive architectural and system-level characterization of real-world On-Line Data Intensive (OLDI) microservices, which aided in building an automated tool that improves microservice performance- and cost-efficiency by customizing hardware and OS knobs for each microservice
Deployed across Facebook's global data center fleet
Triggered modifications in Intel's Alder Lake servers (Golden cove microarchitecture and beyond)
Featured by Facebook Engineering and Real World Technologies
In HPCA 2019 (Acceptance rate: 19.7%)
Amirhossein Mirhosseini, Akshitha Sriraman, Thomas F. Wenisch
A novel heterogeneous server architecture that employs aggressive multithreading to solve the infamous "killer microsecond" problem, without sacrificing the Quality-of-Service of OLDI microservices
In Wild & Crazy Ideas (WACI), 2019
Akshitha Sriraman
Investigates user traits and their correlation with acceptable wait times to design user-specific microservice Service Level Agreements
Best of WACI, Chair's Choice Award
In the Non-Volatile Memories Workshop (NVMW), 2019
Amirhossein Mirhosseini, Akshitha Sriraman, Thomas F. Wenisch
First server architecture to improve server utilization in the presence of µs-scale stalls, without sacrificing QoS and tail latency of microservices
In the Career Workshop for Women and Minorities in Computer Architecture (CWWMCA), 2019
Akshitha Sriraman, Abhishek Dhanotia, Thomas F. Wenisch
Introduces a tool that automatically improves microservice performance- and cost-efficiency by customizing hardware and OS configurations in commodity servers.
In OSDI 2018 (Acceptance rate: 17.8%)
Akshitha Sriraman, Thomas F. Wenisch
Makes the important observation that the latency-optimal microservice threading model or concurrency design choice depends on the offered load, paving the way for an automatic run-time load adaptation system that tunes threading models & scales thread pool sizes to minimize microservice tail latency
In IISWC 2018 (Acceptance rate: 36.1%)
Akshitha Sriraman, Thomas F. Wenisch
Presents the first benchmark suite of end-to-end OLDI services composed of microservices and characterizes their OS and network overheads
In the Workshop on Architectures and Systems for Big Data (ASBD), 2018
Akshitha Sriraman, Thomas F. Wenisch
Suggests how µSuite can be used by researchers to facilitate future research
In the Career Workshop for Women and Minorities in Computer Architecture (CWWMCA), 2018
Akshitha Sriraman, Thomas F. Wenisch
Makes the important observation that inherent latency trade-offs between threading models can be exploited at system run-time to minimize microservice tail latency
In the Career Workshop for Women and Minorities in Computer Architecture (CWWMCA), 2017
Akshitha Sriraman, Thomas F. Wenisch
Makes the important observation that inherent latency trade-offs between threading models can be exploited at system run-time to minimize microservice tail latency
In HPCA 2016 (Acceptance rate: 22%)
Liang Luo, Akshitha Sriraman, Brooke Fugate, Shiliang Hu, Gilles Pokam, Chris J. Newburn, and Joseph Devietti
A novel low-overhead run-time tool that detects cache contention-induced performance bugs and mitigates them using dynamic binary re-writing
In the Workshop on Duplicating, Deconstructing and Debunking (WDDD), 2016
Akshitha Sriraman, Sihang Liu, Sinan Gunbay, Shan Su, Thomas F. Wenisch
Establishes that widely-used network protocol software stacks can significantly degrade OLDI microservice tail latency
Advisor: Prof. Margo Seltzer
Developing a generic hardware-software interface for diverse hardware accelerators
Advisor: Prof. David Brooks
Designing future hardware systems for data centers
Supervisor: Vijay Balakrishnan
Designing custom hardware for diverse microservice functionalities
Supervisor: Abhishek Dhanotia
Analyzing production microservices’ software stacks to understand acceleration opportunities and model speedup in hyperscale systems
Supervisor: Murray Stokely
Developed “soft” SKU—a strategy to maintain hardware fungibility despite significant diversity in bottlenecks across microservices
Supervisor: Abhishek Dhanotia
Comprehensively characterized system-level and architectural bottlenecks across Facebook’s top production microservices
Supervisor: Dr. Ed Nightingale
Developed a bare-metal hypervisor from scratch (including a virtualized MMU) to serve as a defense-in-depth security mechanism for Microsoft Azure Sphere; demonstrated two hypervisor-targeted security attacks and defenses
Supervisor: Dr. Gilles Pokam
Low-overhead run-time tool to detect and mitigate performance degradation caused by the different kinds of cache misses
Advisor: Prof. Joseph Devietti
Run-time detection and mitigation of performance bugs caused by false sharing
Manager: Tajdar Salam
Performance analysis of Windows server platforms
Manager: Madan Lal
Real-time “rotation-per-minute”-based flight warning system for military helicopters/airplanes
Eurosys Doctoral Workshop (EuroDW), 2021
ACM Symposium on Cloud Computing (SoCC), 2020
Young Architect Workshop (YArch-ASPLOS), 2020-2021
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2020
Symposium on Operating Systems Principles (SOSP), 2019
JOBS Workshop at MICRO, 2020
Young Architect Workshop (YArch) at ASPLOS, 2020
Career Workshop for Women & Minorities in Computer Architecture at MICRO, 2019
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2020
Young Architect Workshop (YArch-ASPLOS), 2020
International Symposium on Microarchitecture (MICRO), 2019
EuroSys, 2018, 2019
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2017
IEEE Micro Top Picks, 2018
University of Michigan Ph.D. prospective student visit day, 2018
Explore Grad Studies in CSE Workshop, University of Michigan, 2016
Vidushi Goyal (Ph.D. student at U. Michigan), 2016 - Present
Harini Muthukrishnan (Ph.D. student at U. Michigan), 2016 - Present
Hiwot Tadese Kassa (Ph.D. student at U. Michigan), 2017 - Present
Lillian Pentecost (Ph.D. student at Harvard), 2019 - Present
Katie Lim (Ph.D. student at U. Washington), 2019 - Present
Sara Mahdizadeh Shahri, (Ph.D. student at Penn State), 2019 - Present
Katia Flores (Undergrad at U. Michigan), 2018 - 2019
Linh Le (Undergrad at U. Michigan), 2018 - 2019