Performance Characterization of a Taxonomy of Threading Models for Mid-tier Servers


Modern On-Line Data Intensive (OLDI) applications have evolved from monolithic systems to instead comprise numerous, distributed microservices interacting via Remote Procedure Calls (RPCs). Microservices face sub-millisecond (sub-ms) RPC latency goals, much tighter than their monolithic counterparts that must meet ≥ 100 ms latency targets. Sub-ms–scale threading and concurrency design effects that were once insignificant for such monolithic services can now come to dominate in the sub-ms–scale microservice regime. We investigate how threading design critically impacts microservice tail latency by developing a taxonomy of threading models—a structured understanding of the implications of how microservices manage concurrency and interact with RPC interfaces under wide-ranging loads. We develop μTune, a system that has two features: (1) a novel framework that abstracts threading model implementation from application code, and (2) an automatic load adaptation system that curtails microservice tail latency by exploiting inherent latency trade-offs revealed in our taxonomy to transition among threading models. We study μTune in the context of four OLDI applications to demonstrate up to 1.9x tail latency improvement over static threading choices and state-of-the-art adaptation techniques.

Accepted as a poster in the Career Workshop for Women and Minorities in Computer Architecture held in association with the International Symposium on Microarchitecture (CWWMCA ‘17)
Akshitha Sriraman
Akshitha Sriraman
PhD Candidate

Akshitha Sriraman is a PhD candidate in Computer Science and Engineering at the University of Michigan. Her dissertation research is on the topic of enabling hyperscale web services. Specifically, her work bridges computer architecture and software systems, demonstrating the importance of that bridge in realizing efficient hyperscale web services via solutions that span the systems stack. Her systems solutions to improve hardware efficiency have been deployed in real hyperscale data centers and currently serve billions of users, saving millions of dollars and significantly reducing the global carbon footprint. Additionally, her hardware design proposals have influenced the design of Intel’s Alder Lake (Golden Cove and future generation) CPU architectures. Akshitha has been recognized with a Facebook Fellowship, a Rackham Merit Ph.D. Fellowship, and a CIS Full-Tuition Scholarship. She was selected for the Rising Stars in EECS Workshop and the Heidelberg Laureate Forum. Her research has been recognized with an IEEE Micro Top Picks distinction and has appeared in top computer architecture and systems venues like OSDI, ISCA, ASPLOS, MICRO, and HPCA.